The present invention relates to a read preamplifier for a data transducing system such as a hard disk drive, and more particularly to a read preamplifier that has integrated bias and offset recovery circuitry.
Many microelectronic applications employ systems involving a transducer that generates an electrical system as the result of some external stimulus. The signal generated by the transducer is typically small in magnitude, and thus requires the use of a preamplifier for amplification before signal processing is performed. Furthermore, it is also usually the case that the transducer requires a DC bias for proper operation. Such applications therefore typically include circuitry that serves to both supply bias to the transducer and to provide amplification of the signal generated by the transducer. It is also useful in many applications for this circuitry to be able to transition the transducer bias from an off-state to its steady-state and be capable of linear amplification very rapidly. One such application is a hard disk drive.
The reader circuitry of a preamplifier for a hard disk drive performs two primary functions. One of these functions is to amplify the voltage signal generated by a magneto-resistive transducer (MR head) and deliver this signal with high fidelity to a read channel for data recovery. The second function of the reader is to provide either an accurate DC voltage or current bias to the MR head. While reading data, the MR head (typically modeled as a resistor RMR) can typically be biased at voltage levels between 25 milli-Volts (mV) and 300 mV, or at current levels between 100 micro-Amperes (μA) and 5 milli-Amperes (mA). While writing data, the bias applied to the MR head is usually reduced to a very low value or even to zero for reliability reasons. In the interest of efficiently using the space available on the disk, it is desirable for the reader circuitry to be able to transition the head bias from zero to its full read-mode value very quickly and begin passing data to the read channel. This transition period is referred to in the industry as “write-to-read recovery time.” Currently, state of the art recovery schemes achieve write-to-read recovery times of less than 100 nano-seconds (ns), meaning that the head bias reaches its steady state value so that reading can occur within 100 ns.
For a preamplifier circuit to be considered “recovered” and ready to read data, it has to both establish the proper bias of the MR head and recover (zero-out) the offset created in the data path by the bias change. This figure is usually quantified by specifying a maximum allowable DC baseline error that can exist after the write-to-read recovery period ends.
Traditionally, reader circuits have employed circuitry for biasing the MR head and amplifying the read-back signal that operates essentially independent from one another. In this configuration, the bias circuitry uses a closed-loop feedback system which compares the voltage developed across the head to a fixed reference. The read amplifier also employs a separate feedback loop to recover the offset created by the non-zero head bias. For reasons of stability and head reliability, the sense amplifier operates at a significantly faster speed than the bias loop to prevent bias overshoot. Therefore, the speed at which the head bias can be transitioned is limited by the finite bandwidth of the sense amplifier.
In addition to this limitation, typical preamplifier design requirements also call for the reader to function well over a range of head resistances that can span a ratio range of five to one. This makes the task of providing short write-to-read recovery times for readers that have independent bias and sense amplifier feedback loops rather difficult, since the speed of the bias loop varies directly with RMR while the speed of the sense amplifier loop varies inversely with RMR. Thus, the write-to-read recovery time of a reader architecture that uses an independent bias loop is constrained by its worst-case operating point, which resides at either the minimum or maximum of the RMR spectrum.
Disk drive manufacturers are requesting that preamplifiers have write-to-read recovery times of 50 ns or less. In order to provide a preamplifier that achieves this level of performance, a new architecture is proposed.